学术报告:CCF走进合肥工业大学
发布时间:2023-10-18    发布人:杨武   

报告时间: 20231018日(星期三)9:00-17:00

报告地点:翡翠湖校区科技楼A1712会议室

举办单位:澳门新葡萄新京威尼斯


学术报告(一)

报告人:张吉良

告题目:集成电路硬件安全

工作单位:湖南大学

举办单位:澳门新葡萄新京威尼斯

报告人简介:



张吉良,湖南大学教授,半导体学院(集成电路学院)副院长,国家优秀青年基金获得者,湖南省杰出青年基金获得者、湖南省科技创新领军人才。中国计算机学会容错专委主任。获CCF集成电路Early Career AwardCCF杰出演讲者、湖南省自然科学二等奖(第一),主持国家自然科学基金重点项目、国防科技基础加强计划重点项目等。主要从事信息安全芯片设计、集成电路硬件安全、新型计算架构电路设计等方向研究,以一作或通信发表CCF-A类会议和IEEE/ACM会刊36篇,他连续四年(2020-2023)入选斯坦福大学发布的“全球前2%顶尖科学家”榜单(计算机硬件与体系结构子学科影响力全球排名16)。


学术报告(二)

报告人:温晓青(教授,IEEE Fellow

报告题目:LSI Testing: A Core Technology to a Successful Semiconductor Industry

工作单位:日本九州工业大学

报告简介:

The semiconductor industry is exposed to shrinking feature sizes, growing circuit complexity, increasing clock speeds, and decreasing power supply voltages. In addition to significant impact on LSI design and manufacturing, these factors also have a profound impact on LSI testing, a complex process for separating defective chips from defect-free ones. The major challenges to LSI testing are low test quality, high test cost, and excessive test power. These challenges have led to new chances of innovations in LSI testing, characterized by cell-aware test generation, test compression, and power-aware testing. This talk will review these challenges and chances. Furthermore, this talk will reveal the role of LSI testing in the semiconductor business chain, so as to explain why LSI testing is a core technology to a successful semiconductor industry.  

报告人简介:

Xiaoqing WEN received a B.E. degree from Tsinghua University, China, in 1986, a M.E. degree from Hiroshima University, Japan, in 1990, and a Ph.D. degree from Osaka University, Japan, in 1993. He was an Assistant Professor with Akita University, Japan, frrom 1993 to 1997, and a Visiting Researcher with the University of Wisconsin–Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies Inc., USA, in 1998, and served as its Vice President and Chief Technology Officer until 2003. He joined Kyushu Institute of Technology, Japan, in 2003, where he is currently a Professor of the Department of Computer Science and Networks. He founded Dependable Integarted Systems Research Center at Kyushu Institute of Technology in 2013 and served as its Director until 2015. He is a Co-Founder and Co-Chair of Technical Activity Committee on Power-Aware Testing under Test Technology Technical Council (TTTC) of IEEE Computer Society. He is an Associate Editor for IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and Journal of Electronic Testing: Theory and Applications (JETTA). He co-authored and co-edited two popular books, VLSI Test Principles and Architectures: Design for Testability (2006) and Power-Aware Testing and Test Strategies for Low Power Devices (2009). His research interests include design, test, and diagnosis of VLSI circuits. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Infromation Systmes Society (ISS) of the Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE for his pionerring work in low capture power test generation, a Senior Member of Information Processing Society of Japan (IPSJ), and a Senior Member of IEICE.


学术报告(三)

报告人:Hiroyuki Yotsuyanagi (Professor)

报告题目:On the implementation of boundary scan design with embedded time-to-digital converter in a 3D stacked IC

工作单位:Tokushima University

报告简介:

A defective TSV may cause a small delay that is hard to be detected using logic testing. We have proposed a boundary scan design with an embedded time-to-digital converter circuit to detect delay faults in interconnects. The proposed design was implemented in a prototype 3D IC stacked by TSVs with different diameters. The measurement results show that the proposed delay testable circuit can detect both logic errors that occurred in TSVs with smaller than standard diameters and significant signal delay through a TSV with no logic error.

报告人简介:


Hiroyuki Yotsuyanagi received the B.E., M.E. and Ph.D degrees from Osaka University, in 1993, 1995 and 1998, respectively. He i

s currently an Associate Professor of Division of Science and Technology, Graduate School of Technology, Industrial and Social Sciences, Tokushima University. His research interests include design-for-testability methods for delay testing and post-bond testing of 3D ICs. He is a member of IEICE and JIEP, and a senior member of IEEE.



学术报告(四)

报告人:Senling Wang (Senior Assistant Professor)

报告题目:SASL-JTAG: A Light-Weight Dependable Test Access Mechanism for Edge Devices

工作单位:Ehime University

报告简介:

As the connected devices permeate the human’s daily life, their reliability and security become paramount. JTAG known formally as the IEEE1149.1 Boundary Scan Standard is a widely used test access mechanism for testing, diagnosis and system debugging provides an improved reliability. However, its security vulnerabilities could potentially be a backdoor to cyberattacks, especially in low-performance and cost-sensitive IoT devices. In this work, we propose a lightweight JTAG authentication scheme named the SASL-JTAG, to addresses the performance imbalance issue of IoT systems for enhancing the dependability of edge devices. The architecture of the SASL-JTAG authentication is designed and implemented on an FPGA to verify its functionality and evaluate hardware overhead. SASL-JTAG offers a cost-effective and scalable solution for securing JTAG systems in IoT devices while ensuring high reliability.

报告人简介:


Senling Wang received his M.S and Ph.D. degree from the Department of Computer Science and Electronics at the Kyushu Institute of Technology, Japan, in 2011 and 2014, respectively. Since 2014, he has been with the Graduate School of Science and Engineering at Ehime University, Japan, where he currently serves as the Senior Assistant Professor. His research interests include Field Testing, Low Power Testing, Design for Testability, 3D Stacked IC Testing, and Hardware Security. He is the PI for the Grant-in-Aid for Young Scientists and the Grant-in-Aid for Fundamental Scientific Research, both funded by JSPS. He also serves as the Japanese project leader for a Bilateral Joint Research Project between China and Japan, funded by JSPS and NSFC. Dr. Wang has been a program and committee member for numerous international conferences. He is a member of IEEE, ACM, IEICE, IPSJ, and JIEP.


学术报告(五)

报告人:Hiroshi Kai (Associate Professor)

报告题目:An Evaluation of Computing Time of Simple and Secure Authentication

工作单位:Ehime University

报告简介:

Authentication of IoT devices is important to achieve secure communication in data communication between IoT devices and servers. In this study, we evaluate the processing time on a single-board computer for SAS-L1 and SAS-L2, which reduce the computational cost of the lightweight one-time password authentication method SAS-2.

报告人简介:

Hiroshi Kai received the B.E., M.E., and Doctor of Engineering degrees from Ehime University, in 1992, 1994 and 1999, respectively.
He is currently an Associate Professor of Department of Computer
Science, Graduate School of Science and Engineering, Ehime University. His Research Interests include algorithms for computer algebra system, hybrid symbolic-numeric computation, information security. He is a member of ACM, IEEE, and Japanese societies IPSJ and JSSAC.



学术报告(六)

报告人:Stefan Holst (Associate Professor),

报告题目:Tackling Test and Diagnosis Challenges Using GPU-Based High-Throughput Timing Simulation

工作单位:Kyushu Institute of Technology

报告简介:

The extreme compute demand of Machine-Learning (ML) applications pushes the development of ever more powerful Data-Parallel AI Accelerators. This talk explains how to leverage these Compute Accelerators to achieve High-Performance VLSI Timing Simulations, a core component of Electronic Design Automation (EDA) tools needed for the development and analysis of today's complex System-on-Chips. This timing simulator delivers performances several orders of magnitude higher than conventional approaches and enables many new applications. This talk shows three example applications from the fields of scan-test power analysis, small delay fault simulation and diagnosis, as well as AI accelerator resilience analysis.

报告人简介:


Stefan Holst received his PhD in 2012 from University of Stuttgart, Germany, under supervision of Prof. Hans-Joachim Wunderlich. In 2013, he joined Kyushu Institute of Technology (Japan) where he is now an associate professor in the Department of Computer Science and Networks. He published over 50 works in journals, at international conferences and at peer-reviewed workshops and received three best paper awards (ETS2007, ATS2015, ATS2021). His research interests include reliability of AI hardware, VLSI simulation and diagnosis, soft-error tolerance as well as power-aware test.




学术报告(七)

报告人:马瑞君

报告题目:A Novel High Performance Scan-Test-Aware Hardened Latch Design with Improved Soft-Error Tolerability

工作单位:安徽理工大学

报告简介:

The continuous pursuing of smaller technology nodes makes modern Integrated Circuits (ICs) more and more susceptible to soft-errors. Many radiation-hardened latch designs have been proposed to tolerate soft-errors for reliable LSI designs. However, these existing hardened latches can suffer from reliability issues after production because production defects in such hardened latches are difficult to detect with conventional scan testing. In our previous works, we improved the defect detectability of these hardened latches by adding design-for-test (DFT) technique. A hardened latch design, called high performance scan-test-aware hardened latch (HP-STAHL), was proposed for higher defect detectability, higher soft-error tolerability, and lower propagation delay. However, the added DFT structure in HP-STAHL can partially reduce its soft-error tolerability. In this paper, we propose a novel high performance scan-test-aware hardened latch design with improved soft-error tolerability (HP-STAHL-I) by applying a novel design to offset the reduced soft-error tolerability. Simulation results show that HP-STAHL-I provides higher soft-error tolerability than HP-STAHL. HP-STAHL-I also has lower delay and power delay product (PDP) than the standard latch, demonstrating its high performance.

报告人简介:



马瑞君,博士毕业于日本九州工业大学,现任职于安徽理工大学计算机科学与工程学院,主要研究方向:软错误、加固锁存器设计、可测试性设计等。





学术报告(八)

报告人:宋钛

报告题目:Cutting Costs in IC Testing with Machine Learning

工作单位:安徽大学

报告简介:

As the size of VLSI circuits continues to shrink and lithography technology advances, the complexity of system-on-chip (SoC) design, system packaging, power management strategies, and signal integrity issues are becoming increasingly prominent, resulting in increased testing time and costs for the entire circuit system. The key challenge in today's testing process is how to reduce integrated circuit testing costs without compromising testing quality. To achieve the optimal solution between testing costs and testing quality, research on integrated circuit testing vector optimization methods is necessary. To address the critical issues of testing time, testing costs, testing quality, and fault coverage that are urgently needed in testing, research is conducted in areas such as machine learning, data mining, database establishment, and vector optimization to achieve cost savings in testing.

报告人简介:


Tai Songreceived the Dr.-Ing. degree in Microelectronics from Hefei University of Technology, China since 2020. As a joint doctoral student, he visited the University of Stuttgart, Baden-Württemberg, Germany, from 2019 to 2020. Since 2021, he has been a full-time teacher working in the School of Integrated Circuits of Anhui university, China. For the last few years, his work has been mainly focused on VLSI test, IC reliability, machine learning, Hardware Trojan detection, Chiplet design and test. Some of the leading scientific journals he has published include IEEE VTS, JETTA, Integration the VLSI and thehonour of best paper for CFTC2023. These publications can be found at: [https://orcid.org/0000-0002-7082-4211]. (Based on document published on 12 October 2023) 



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